For more than 40 years, semiconductor technology has followed Moore’s Law — the principle that miniaturization, or scaling, drives improved performance.

At the 3nm and 2nm nodes, however, physical limits and quantum effects have become significant barriers, making it increasingly difficult to continue improving performance simply by extending this same trajectory.

In this section, we’ll examine:

・Why miniaturization is approaching its limits

・What new operating principles will be needed going forward

・90nm → 65nm → 45nm → 32nm → 22nm → 14nm → 10nm → 7nm → 5nm → 3nm → 2nm

・MOSFETs shifted from planar structures to FinFET starting around the 22nm node.

・They have since progressed further to GAA (Gate-All-Around) structures starting around the 2nm node.

Miniaturization delivered improved logic performance and lower power consumption for decades, but it is now facing a sharp deceleration.

3-1. Short-channel effects

When the gate becomes too short, several problems emerge:

・The drain’s electric field begins interfering with the source side.

・Current leaks even when the device is supposed to be OFF.

・The threshold voltage (Vth) becomes unstable.

In effect, MOSFETs become increasingly difficult to control precisely.

3-2. A sharp rise in leakage current

As the gate insulating layer becomes thinner, electrons increasingly tunnel through it, causing leakage current to rise.

・This causes standby power consumption to spike.

・It worsens power-related challenges in smartphones and servers alike.

3-3. The emergence of quantum effects

At scales below 2nm, electrons increasingly behave as waves rather than particles.

・Tunneling currents

・Quantum fluctuations

・Changes in effective mass

・Changes in energy band structure

As a result, the classical physics underlying traditional MOSFET theory begins to break down.

3-4. Increasing wiring resistance and RC delay

Even as the MOSFET itself shrinks, the resistance and capacitance of the wiring (the metal layers) are approaching their own limits.

・Signal delay (RC delay) becomes a bottleneck.

・This effect is particularly pronounced in AI chips, where communication with memory has grown substantially.

3-5. Thermal challenges (heat generation and cooling)

Miniaturization means higher density — and higher density leaves less room for heat to escape. This has become an increasingly urgent problem in AI servers.

Because miniaturization alone is no longer sufficient, structural innovation has become essential.

4-1. FinFET

・Features a fin-shaped channel.

・The gate controls the channel from three directions, suppressing short-channel effects.

FinFET has been the mainstream structure since the 22nm node.

4-2. GAA (Gate-All-Around) nanosheet FET

・The gate wraps completely around the channel, covering all 360 degrees.

・The mainstream structure at the 2nm node.

・Channel width can be adjusted, offering high design flexibility.

This structure suppresses short-channel effects more effectively than any prior approach.

4-3. CFET (Complementary FET)

・Stacks N-channel and P-channel devices vertically, one atop the other.

・Dramatically shortens wiring distances.

CFET is considered the leading candidate for future 3D logic structures.

Going forward, semiconductor progress can no longer rely on miniaturization alone. As a result, researchers are exploring new operating principles that could support the industry in a post-Moore’s-Law world.

5-1. TFET (Tunnel FET)

・Current flows via the tunneling effect.

・Capable of operating at ultra-low voltages, around the 0.3V range.

・A leading candidate for low-power chips.

・Weakness: relatively low ON current.

5-2. Spintronic devices

These devices make use of an electron’s spin rather than its charge. Examples include:

・MRAM (already in practical use as non-volatile memory)

・Spin-FET (still at the research stage)

Benefits include high speed, non-volatility, and high durability, making these devices promising for AI and server applications.

5-3. Ferroelectric FET (FeFET)

・Uses a ferroelectric material as the gate insulator.

・Can retain its state without relying on stored charge, enabling ultra-low power consumption, high speed, and non-volatility.

・A promising technology for merging next-generation memory and logic.

5-4. Photonic devices

These devices compute and transmit using light rather than electrons. Examples include:

・Silicon photonics

・Optical interconnects

Benefits include ultra-high speed (approaching the speed of light), low loss, and reduced heat generation, making this a promising technology for overcoming the wiring limitations facing AI servers.

5-5. Quantum devices

・Operate at the level of controlling individual electrons.

・Enable the realization of quantum bits (qubits).

・Capable of massively parallel computation.

Applications include cryptography, materials discovery, and optimization problems, though many challenges remain before large-scale practical deployment.

As miniaturization slows, the industry is increasingly turning to 3D stacking and chiplet architectures to continue improving performance.

・TSV stacking (Through-Silicon-Via)

・Chiplets (used by AMD and Intel)

・HBM (High Bandwidth Memory)

・CoWoS (TSMC)

・SoIC (TSMC’s 3D logic technology)

This direction is sometimes referred to not as “Moore’s Law” but as “More than Moore” — a systems-level path to continued progress.

Miniaturization has now entered the 2nm node, and its physical limits have finally become a practical reality. To push past these limits, the industry is advancing along several fronts:

1.Structural innovation (FinFET → GAA → CFET)

2.New operating-principle devices (TFET, spintronics, FeFET)

3.The introduction of photonic technology (silicon photonics)

4.3D integration and chiplet architectures

5.The pursuit of quantum devices

1.Name two of the main reasons miniaturization is approaching its limits.

2.What are the advantages of the “GAA structure” adopted at the 2nm node?

3.What technologies represent approaches other than miniaturization?

 

Column Supervisor: Koji Kakumoto (Otis Group Co., Ltd.)

After studying abroad and working in planning and development at a trading company, he joined Otis Group Co., Ltd. in 2011. While primarily working in the Corporate Planning Department, he has also served concurrently in manufacturing and technical divisions, and since 2018 has served as Representative Director, working to drive business growth and strengthen the organization.

 

This article is a general technical explanation intended for educational purposes and does not refer to any specific company, product, or technology.