Flash memory is a type of non-volatile memory that can be electrically rewritten and that retains data even when power is turned off. It first emerged in the 1980s and has since become the central technology behind virtually every kind of storage device, including smartphones, SSDs, and USB flash drives.

 

The name “flash” comes from its ability to erase large blocks of data all at once, at high speed.

Each bit cell in flash memory is built from a specialized type of MOSFET, distinguished by its floating gate.

 

Overview of the structure:

・A “floating gate” layer, designed to trap electrons, is inserted within the oxide layer of a standard MOSFET’s gate.

・Injecting or removing electrons from this layer records the presence or absence of charge.

・Depending on the specific scheme used, the presence of charge is interpreted as either a “1” or a “0.”

 

Electrons are moved in and out of the floating gate using mechanisms such as the Fowler-Nordheim tunneling effect or hot-carrier injection.

During a write operation, electrons are injected into the floating gate:

1.A high voltage (roughly 10–20V) is applied to the gate.

2.Electrons tunnel through the oxide layer and accumulate in the floating gate.

3.The accumulated electrons raise the cell’s threshold voltage (Vth).

4.The cell is then read as representing a “1” (or “0,” depending on the convention used).

Erasing works in the opposite direction, removing electrons from the floating gate:

・A high voltage is applied in the reverse direction, pulling electrons back out through the oxide layer.

・The threshold voltage (Vth) returns to its original level, resetting the cell.

・In flash memory, erasing is performed collectively across an entire block of cells.

 

This is precisely why the technology is called “flash” — data is erased in one quick, sweeping operation.

During a read operation, a low voltage (roughly 1V) is applied to the gate to detect whether current flows:

・If electrons are trapped in the floating gate → the channel remains closed and no current flows.

・If no electrons are present → the channel opens and current flows.

 

This difference is what allows the cell to be read as either a 0 or a 1.

In NOR-type flash, cells are connected in parallel, allowing each individual cell to be accessed directly.

Characteristics:

・Each cell can be read from and written to independently.

・Read speed is fast.

・Well suited to random access.

 

Drawbacks:

・Cell area is relatively large, making it poorly suited to large capacities.

・Writing and erasing are relatively slow.

 

Applications: Firmware ROM, microcontroller-embedded ROM, code storage.

In NAND-type flash, cells are connected in series and accessed in blocks.

Characteristics:

・Small cell area, well suited to achieving large capacity.

・Writing and reading occur in units called pages (a few KB to a few dozen KB).

・Erasing occurs in units called blocks (a few MB).

・Read speed is slower, but the technology is well suited to storage applications.

 

Applications: SSDs, USB flash drives, SD cards, and internal storage in smartphones.

Flash memory is classified based on how many bits are stored in each cell:

・SLC (Single-Level Cell): 1 bit per cell (fast, highly reliable, but expensive)

・MLC (Multi-Level Cell): 2 bits per cell (moderate performance and cost)

・TLC (Triple-Level Cell): 3 bits per cell (large capacity and inexpensive)

・QLC (Quad-Level Cell): 4 bits per cell (extremely high density, but lower endurance)

 

Today, techniques such as “SLC caching” and hybrid configurations are commonly used, tailored to the specific application.

Cells were traditionally arranged in a flat, planar layout. In recent years, however, “3D NAND” — which stacks cells vertically across many layers — has become the mainstream approach.

Characteristics:

・Layer counts have progressed to 128, 176, and now beyond 200 layers.

・Storage density has improved dramatically.

・Both cost reduction and speed improvements have been achieved simultaneously.

 

Examples include Samsung’s “V-NAND,” Kioxia/WD’s “BiCS,” and Micron’s “3D NAND.”

・A limited number of write/erase cycles (limited endurance)

・Declining write speed, particularly with TLC and QLC

・The need for error correction (ECC) circuitry

・The management burden created by the mismatch between write units and erase units (requiring wear leveling)

The flash controller plays a critical role in managing these challenges.

・Research is underway into the successor to QLC: PLC (5 bits per cell).

・Further increases in the number of stacked layers — potentially beyond 500 — are on the horizon.

・Concepts for a “universal memory,” merging flash with technologies like MRAM and ReRAM, continue to develop.

・AI-driven prediction of cell lifespan and optimization of error correction are becoming increasingly practical.

・Flash memory is a non-volatile memory type that can be electrically erased and rewritten.

・NOR type: fast read speed, lower density.

・NAND type: large capacity, low cost, well suited to storage.

・Advances in 3D structuring and multi-level cells (from SLC to QLC) continue to improve both performance and cost.

・The next generation is expected to bring further evolution through PLC and new materials-based devices.

1.What is the “floating gate” in flash memory?

2.What is the structural difference between NAND-type and NOR-type flash?

3.What is the biggest advantage of 3D NAND technology?

 

Column Supervisor: Koji Kakumoto (Otis Group Co., Ltd.)

After studying abroad and working in planning and development at a trading company, he joined Otis Group Co., Ltd. in 2011. While primarily working in the Corporate Planning Department, he has also served concurrently in manufacturing and technical divisions, and since 2018 has served as Representative Director, working to drive business growth and strengthen the organization.

 

This article is a general technical explanation intended for educational purposes and does not refer to any specific company, product, or technology.