Dicing is the process of cutting apart the individual, completed chips arranged across a wafer, separating them one by one.

In essence, this step marks the transition from a “wafer” — the product of front-end processing — into individual “chips,” ready for back-end processing.

Although this process may sound simple, it’s actually one of the steps most prone to cracking, chipping, and other physical damage.

Before dicing, the wafer is still relatively thick, so the following preparation steps are essential:

(1) Back grinding (BG)

・Thins the wafer, typically from around 725μm down to 100μm or even 50μm.

・Chips used in smartphone SoCs and memory devices are often extremely thin.

・The thinner the wafer, the more prone it becomes to cracking, requiring highly precise control.

 

(2) Dicing tape mounting

To prevent the now-thin wafer from falling apart, it is affixed to an adhesive tape before cutting begins.

(1) Blade dicing (the most common method)

Cuts the wafer using a thin, rotating blade coated with diamond abrasive particles.

Characteristics

・Fast and low cost

・The standard method for many products

・However, prone to physical damage such as chipping

 

(2) Laser dicing

Cuts by using a laser to form a groove along the cutting line.

Characteristics

・Non-contact process, resulting in less chipping

・Fast processing speed

・Compatible with silicon, SiC, and glass substrates

・Managing thermal effects is important

 

(3) Stealth dicing (SD)

Increasingly the mainstream method in recent years. A laser is focused inside the silicon itself, weakening the material internally so that it can then be cleanly separated using external force.

Characteristics

・Leaves the surface undamaged

・Minimizes damage to the device

・Growing adoption in 3D NAND and power devices

・Particularly advantageous for thinner wafers

 

Stealth dicing is currently considered the most reliable dicing method available.

Defects that occur during dicing directly affect the yield of subsequent back-end processing.

Representative defects include:

・Chipping: material breaking away from the edge

・Cracking: fractures forming within the material

・Microcracks: fractures too small to see with the naked eye

・Particle contamination: leftover debris from the cutting process

・Damage occurring during tape removal

 

Internal cracks are especially dangerous, since they can lead to failure later, during subsequent temperature cycling.

Dicing quality depends on several key parameters:

・Blade rotation speed

・Table feed speed

・Cutting depth

・Cooling water (flow rate and temperature)

・Tape adhesive strength

・Wafer thickness

・Material type (Si, SiC, GaN)

 

Because SiC and GaN are extremely hard materials, stealth dicing proves especially effective for these substrates.

This is the step in which individual chips are lifted off the tape once cutting is complete.

Key quality factors

・Flatness of the chip’s back surface

・How easily the tape releases

・Whether any cracks are present

・Chip size (larger chips are more prone to damage)

 

If a chip is damaged during this step, all of the effort invested during front-end processing is wasted.

Recent challenges include:

・Wafers becoming extremely thin and increasingly prone to cracking

・Low-k dielectric films being inherently brittle

・Power device substrates being hard and difficult to process

・The growing impact of particle contamination

・Increasing chipping risk in areas with dense wiring

 

As a result, laser-based and stealth dicing methods are rapidly becoming the mainstream approach.

Current trends in dicing include:

・Mass production adoption of stealth dicing

・Plasma dicing (a non-contact etching-based approach)

・Specialized tape for ultra-thin wafers

・Water-free laser dicing (for improved environmental impact)

・AI-based image analysis for crack detection

・High-speed laser dicing tailored for SiC power devices

 

The key themes for the next generation are: no chipping, no cracking, and no physical contact.

・Dicing is the process of cutting a wafer into individual chips.

・The three main methods are blade dicing, laser dicing, and stealth dicing.

・Stealth dicing causes the least damage and is becoming the next-generation standard.

・Chipping and cracking are critical defects that directly affect reliability.

・The difficulty of dicing continues to increase year by year as wafers grow thinner.

・The future direction lies in combining AI with non-contact processing methods.

1.What does the dicing process actually do?

2.Explain the difference between the blade method and the stealth method.

3.Name one of the most significant defects that can occur during dicing.

 

Column Supervisor: Koji Kakumoto (Otis Group Co., Ltd.)

After studying abroad and working in planning and development at a trading company, he joined Otis Group Co., Ltd. in 2011. While primarily working in the Corporate Planning Department, he has also served concurrently in manufacturing and technical divisions, and since 2018 has served as Representative Director, working to drive business growth and strengthen the organization.

 

This article is a general technical explanation intended for educational purposes and does not refer to any specific company, product, or technology.