Transistor sizes have now reached an extremely small range of a few nanometers.

At this level, various problems become apparent with conventional semiconductor design.

Main challenges:

・Increasing leakage current

・Current leakage due to quantum tunneling

・Increasing heat generation

・Increasing wiring resistance

The smaller transistors become, the more the behavior of electrons is influenced by quantum mechanics rather than classical physics, making control more difficult.

Another premise of Moore’s Law is “cost reduction.” In leading-edge processes, however, this premise has also begun to break down.

Main factors:

・Rising prices of EUV lithography equipment

・Increasing complexity of manufacturing equipment

・Increasing development costs

For example, a single EUV lithography tool is said to cost more than 20 billion yen, and the construction cost of a leading-edge semiconductor factory can reach the scale of 2 trillion yen.

For this reason, the companies capable of manufacturing leading-edge semiconductors are currently limited almost entirely to TSMC, Samsung, and Intel.

To cope with the limits of scaling, the structure of the transistor itself is also evolving.

Main structural changes:

・Planar transistors

・FinFET (three-dimensional transistors)

・GAAFET (Gate-All-Around)

GAAFET is a structure in which the gate completely surrounds the channel, which improves current control performance.

This structure is expected to become mainstream in future processes of 3nm and below.

Various approaches are being researched as technologies that do not rely solely on transistor scaling.

Representative examples:

・Advanced packaging (2.5D / 3D)

・Chiplet architecture

・Higher bandwidth with HBM memory

・Dedicated accelerators (AI chips)

These are also called “More than Moore” and are approaches that aim to improve the performance of the system as a whole.

Until now, semiconductor performance was determined by “how many transistors can be packed in.” Today, however,

system integration technology that combines multiple elements such as

・Chips

・Packages

・Memory

・Interconnects

has become important.

In AI chips and processors for data centers, this integration technology has become an important factor that determines performance.

・Moore’s Law is approaching its physical and economic limits

・Transistor structures are evolving from FinFET to GAAFET

・Semiconductor performance cannot be improved by scaling alone

・Advanced packaging and chiplets play important roles

1.Why is transistor scaling becoming more difficult?

2.What impact does EUV lithography equipment have on semiconductor manufacturing costs?

3.What kind of approach is “More than Moore”?

 

Column Supervisor: Koji Kakumoto (President, OTIS Co., Ltd.)

After studying abroad and working in planning and development at a trading company, he joined OTIS Co., Ltd. in 2011. While primarily working in the Corporate Planning Department, he has also served concurrently in manufacturing and technical divisions, and since 2018 has served as President, working to drive business growth and strengthen the organization.

 

This article is a general technical explanation intended for educational purposes and does not refer to any specific company, product, or technology.