With wire bonding, problems arise such as:

・Long wiring lengths

・High inductance

・Weakness with high-speed signals

・Limits on the number of I/Os

However, SoCs, GPUs, and AI chips face overwhelming demands such as:

・Thousands to tens of thousands of I/Os

・Ultra-high-speed signals (GHz range)

・High current

・Enormous heat generation

so wire bonding can no longer cope.

This is where flip chip came in.

Features:

・Shortest wiring length → high-speed signals, low noise

・Greatly increased number of I/Os

・Power/GND can be distributed, improving power quality

・Heat can be dissipated across the entire chip surface

・High-density mounting

As a result, nearly all high-end devices have moved to flip chip.

The core technology that determines flip chip performance is the bump.

(1) C4 Bumps (Conventional Solder Bumps)

Material: Sn-Ag-Cu (Pb-free)

Advantages:

・Highly reliable with a long track record

・The process is mature

Challenges:

・Limits to fine-pitch scaling (<40 µm is difficult)

・Resistance increases in high-current applications

(2) Copper Pillars

Currently the most rapidly spreading method.

Structure: A thin Sn layer is formed on the tip of a Cu pillar → bonded by reflow

Advantages:

・Supports fine pitches (20–40 µm)

・Strong under high current × high heat × high density

・Mainstream in large-scale AI/GPU chips

Challenges:

・Coplanarity control is difficult

・A process to prevent Cu oxidation is required

(3) Microbumps (for HBM / 2.5D)

Features:

・Ultra-fine bumps in the 10 µm class

・Combined with TSVs to form high-bandwidth memory (HBM)

Challenges:

・A single defect can lead to “the loss of an entire multi-die stack”

→ Yield is overwhelmingly important

In flip chip, the difference in thermal expansion between the chip and the substrate is large, so bumps are prone to fatigue and cracking.

What solves this problem is underfill (resin).

Roles:

・Absorbing thermal cycling stress

・Strengthening resistance to drop impact

・Preventing bump failure

・Improving the heat conduction path (high-thermal-conductivity underfills also exist)

Because the quality of the underfill determines reliability, collaboration with material manufacturers is essential.

(1) Poor Coplanarity

Variation in bump height → bonding failures

(2) Voids

Cavities formed during underfill injection → become crack initiation points

(3) Contamination / Oxidation of Substrate-Side Pads

→ Poor wettability prevents bonding

(4) Heat Problems

In flip chip, the chip’s back side faces up, so in AI chips, heat density becomes a bottleneck.

(5) High-Frequency and Power Supply Noise

SI/PI/EMI vary with bump placement → analysis and simulation are essential

・Strong with high-speed signals (shortest wiring length)

・Power/GND can be taken over an area → improved power quality

・Supports a large number of I/Os

・Advantageous for heat dissipation

・Essential for miniaturization

・Highly compatible with HBM, chiplets, and 2.5D/3D

It is fair to say that GPUs, AI chips, and HBM in particular could not exist without flip chip.

1.Form UBM (under bump metallization) on the wafer

2.Form bumps (C4 / Cu pillars, etc.)

3.Dicing

4.Pick & place

5.Reflow bonding to the substrate side

6.Underfill filling

7.Molding

8.Testing

There are many process steps, and yield depends on multiple steps.

Cu pillars becoming mainstream

Cu matches the current levels of the AI era.

Stronger integration with redistribution layers (RDL)

Integrated with fan-out / 2.5D.

Strengthened as a foundational technology for advanced packages such as CoWoS / InFO

Combined use of TIMs and vapor chambers to solve heat problems

Shift from microbumps → hybrid bonding (direct bonding)

(Progressing at TSMC, Intel, and Samsung)

Flip chip is the core technology that meets leading-edge requirements of:

・High speed × high density × high heat

・High current × wide bandwidth

Evolving from C4 → Cu pillars → microbumps → hybrid bonding, it has become the foundation supporting the era of HBM, AI chips, and chiplets.

1.Why is flip chip better suited to high-speed signals than wire bonding?

2.Name one main advantage of adopting Cu pillars.

3.Why is underfill essential?

 

Column Supervisor: Koji Kakumoto (President, OTIS Co., Ltd.)

After studying abroad and working in planning and development at a trading company, he joined OTIS Co., Ltd. in 2011. While primarily working in the Corporate Planning Department, he has also served concurrently in manufacturing and technical divisions, and since 2018 has served as President, working to drive business growth and strengthen the organization.

 

This article is a general technical explanation intended for educational purposes and does not refer to any specific company, product, or technology.