WLP (Wafer Level Package) is a method that achieves a package nearly the same size as the chip.

As the name “fan-in” suggests, it is a structure in which the terminals (balls) fit within the area of the chip.

Features

・Ultra-compact (ideal for smartphones and IoT)

・Everything through mounting is completed at the wafer level → low cost

・Short wiring lengths and strong high-frequency performance

・Very thin package

Challenges

・Low upper limit on the number of I/Os

・Difficult to apply as chip size increases

・Weak heat spreading, unsuitable for high-heat devices

Example applications: PMICs, RF, sensors, mobile peripheral ICs.

Fan-out is a technology created to solve the drawback of WLP (a small number of I/Os).

Features:

● Resin (molding) is formed around the chip, and a redistribution layer (RDL) is built on top of it, fanning out (spreading) the terminals beyond the chip size.

Results:

・The number of I/Os can be greatly increased

・The package can be made compact

・High wiring performance, also good for RF characteristics

(1) Reconstituted Wafer

The most common method.

1.Chips are embedded in resin to create a “reconstituted wafer”

2.RDL (redistribution layer) formation

3.Bump formation

4.Package completion

Fan-out was also adopted for Apple’s A-series chips, and spread rapidly in the smartphone market.

(2) Panel Level Package (PLP)

A method that processes fan-out on large-area panels.

Advantages:

・Panel size → higher productivity

・Large cost-reduction effect

Challenges:

・Panel warpage

・RDL uniformity

・Equipment standardization has not been established

It is seen as the area expected to grow the most in the future.

Item	Fan-in (WLP)	Fan-out (FO-WLP)
Number of I/Os	Few	Many (greatly increased)
Package size	Same as the chip	Can be larger than the chip
Cost	Low	Higher than WLP
Thermal performance	Weak	Can be improved
High-frequency characteristics	○	◎
Applications	PMICs, RF, sensors	Mobile SoCs, APs, AI edge, RF

Conclusion:

・Compact & low cost → fan-in

・High I/O & high performance → fan-out

The performance of fan-out is determined by RDL technology.

What is RDL?

・A fine wiring layer using Cu and polyimide

・A technology that reroutes the chip’s pad positions outward to create outputs

Key elements:

・Finer L/S (line / space)

・Uniformity of sputtering → electroplated Cu → CMP

・Insulating films that do not crack

・Interface reliability with the substrate

RDL yield governs most of the package yield.

(1) Warpage

Warpage occurs due to the CTE difference between the resin and the chip → the RDL cracks

(2) RDL Cracks / Disconnections

Stress tends to concentrate in the thin films

(3) Uniformity of Resin Molding

Voids directly affect yield

(4) Chip Misalignment

Chip coordinate shifts in the reconstituted wafer → RDL defects

(5) Thermal Reliability

Weak against heat from power devices → thermal design is important

The key to fan-out success is the triangular balance of RDL × resin × heat.

Active adoption by Apple / Qualcomm

Established in smartphone applications and expanding into other markets.

Accelerating volume production of FO-PLP (panel level)

Samsung, ASE, and SPIL are leading the way.

High-performance fan-out for AI edge

Demand is growing due to more I/Os and improved RF characteristics.

Fusion of chiplets × fan-out

Research is progressing on connecting multiple chips without an interposer.

Combination with hybrid bonding

Toward next-generation high-density packaging technology.

Fan-in (WLP) → For ultra-compact devices. Fewer I/Os, low cost.

Fan-out (FO-WLP) → A next-generation package that achieves more I/Os × higher performance. RDL is the core technology, and warpage, stress, and yield are what matter.

Fan-out will become even more important in the future for smartphone SoCs, RF, AI edge, and chiplet interconnection.

1.What is the biggest structural difference between fan-in and fan-out?

2.Explain why the RDL (redistribution layer) is important in fan-out.

3.Name one factor that makes fan-out prone to yield loss.

 

Column Supervisor: Koji Kakumoto (President, OTIS Co., Ltd.)

After studying abroad and working in planning and development at a trading company, he joined OTIS Co., Ltd. in 2011. While primarily working in the Corporate Planning Department, he has also served concurrently in manufacturing and technical divisions, and since 2018 has served as President, working to drive business growth and strengthen the organization.

 

This article is a general technical explanation intended for educational purposes and does not refer to any specific company, product, or technology.